Semiconductor chip carrier affording a high-density external interface
US6577003B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2000 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Oct 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3421
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts. A semiconductor die carrier may also include an insulative substrate; a plurality of leads each having an external portion extending out of the semiconductor die carrier from a lower surface of the insulative substrate and an internal portion located within the semiconductor die carrier at an upper surface of the insulative substrate; a semiconductor die; and a layer of conductive material in contact with conductive portions of the semiconductor die and also in contact with the internal portions of the leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.