Self timing interlock circuit for embedded DRAM
US6577548B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for a self timed DRAM. The circuit includes interlock circuits coupled to an extension of the DRAM. The extension does not store “real” data but mimics the operations of the DRAM. The interlock circuits, in conjunction with the extension monitor and control read and write timings of the DRAM and self adjust these timings via feedback. To properly track DRAM cell timings, the interlock circuits and extension use the same cell design and load conditions as the DRAM. The method includes: activating a wordline and reference wordline, interlocking the sense amplifiers, column select and write back functions of the primary DRAM array by monitoring the identical reference cells and the state of the bitline in the extension DRAM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.