Timing recovery system for a 10 BASE-T/100 BASE-T ethernet physical layer line interface
US6577689B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1999 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Apr 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase lock loop is provided for recovering timing information from a received data signal in a 100Base-TX receiver. The phase lock loop includes a phase encoder (803) for generating a reference phase error. An output phase value on a bus (809) is subtracted from the reference phase value on line (805) with a subtraction block (813) to generate a phase error. This phase error is averaged and decimated over a predetermined number of potential symbol transitions in the received signal. The output phase error is provided from a block (815) on a line (817) to a loop filter. This output is provided only once for each decimation operation such that the loop filter can operate at a lower clock rate. The phase error output is then utilized to select one of multiple clocks that correspond to the phase error, these being incremental phase clocks referenced to a master clock. This utilizes a clock multiplexer (1427) to select one of the multiple clock inputs which are delayed in phase off of the master clock. This selection is synchronized with the receive clock output of the multiplexer (1427) with the original output phase converted to gray encoded values. The ensures that only a single bi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.