Data processing system with adjustable clocks for partitioned synchronous interfaces
US6578155B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2000 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Mar 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system (20) having a synchronous interface and partitioned clock and I/O logic controller structure. The system includes a plurality of processing components (22), each having a plurality of I/O logic controllers (24). In addition, the system includes a plurality of clock sources (30) for providing clock signals and a plurality of multiplexers (36) connected to said plurality of clock sources and to at least two of said I/O logic controllers. The clock signals differ from one another in frequency or in skew, i.e., time delay. By appropriate control of clock select registers connected to the plurality of multiplexers, one of the plurality of clock signals from the clock sources may be provided to the two or more I/O logic controllers connected to a given multiplexer. This permits different groups of I/O logic controllers to receive different clock signals in parallel. As a consequence, the signal interface for the system is partitioned into multiple group with each group controlled by a separate clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.