Processes for chemical-mechanical polishing of a semiconductor wafer
US6579798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2001 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Oct 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer. The process also includes the steps of simultaneously buffing a second wafer with the buffing pad for a second length of time, in which the first length of time is greater than the second length of time, and rinsing the buffing pad and the buffed wafer with a moisture maintenance compound for at least a portion of the time between the completion of the second length of time and the first length of time. Moreover, th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.