Double sidewall short channel split gate flash memory
US6580116B2 · kind B2 · utility
9Cited by
20References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Nov 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
An electrically programmable read only memory device which has efficiency of electron injection from channel to floating gate is provided. This memory cell includes a control gate and floating gate between source and drain regions. The region under the floating gate has extremely small enhanced mode channel and N region. Therefore, this channel is completely depleted by the program drain voltage. The enhanced mode channel region is precisely defined by the side wall spacer technique. Also, the N drain region is accurately defined by the difference of side wall polysilicon gate and the first spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.