Boost circuit with normally off JFET
US6580252B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2001 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Jun 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/87
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An enhancement mode JFET as a switching device in a boost converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocking state. The ratio of converter dc output voltage to converter dc input voltage is determined by the ratio of JFET conducting time to the sum of JFET conducting time and JFET blocking time. This pulse width modulation scheme is thus used to adjust the dc output voltage level. Limits on both frequency of operation and duty cycle result from slow switching speeds. Each time a device switches between states, a certain amount of energy is lost. The slower the device switching time, the greater the power loss in the circuit. The effects become very important in high frequency (fast switching) and/or high power circuits where as much as 50% of the losses are due to excessive switch transition time. The enhancement mode JFET is an excellent switch since it has a very small internal resistance between source and drain in the conducting state as well as a very small terminal voltage. As a result, very little power is dissipated in the JFET…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.