Body-contacted and double gate-contacted differential logic circuit and method of operation

US6580293B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kerry Bernstein · Underhill, US
• Peter E. Cottrell · South Burlington, US
• Stephen V. Kosonocky · Fort Collins, US
• David Meltzer · Wappingers Falls, US
• Edward J. Nowak · South Burlington, US
• Kevin John Nowka · Round Rock, US
• Norman J. Rohrer · Underhill, US

Key dates

• Filing date: Dec 14, 2001
• Grant date: Jun 17, 2003
• Expiry date: Dec 14, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K3/356113
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.