Memory circuit
US6580648B1 · kind B1 · utility
3Cited by
8References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Mar 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory having sense amplifiers and data latches, the data latches being used in a test mode to form a signature register. In a normal operation mode, the data latches are form write data latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.