Latching annihilation based logic gate
US6583650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Jan 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a precharge circuit that has a first precharged node, a second precharged node, and a latch device. The first precharged node is charged to a high value during a precharge state. In response to a transition from the precharge state to an evaluate state, it either discharges to a low value or remains charged at its high value. The second precharged node has a value in the evaluate state that is based on the value of the first precharged node upon the circuit transitioning to the evaluate state. The latch device is connected to the second precharged node for latching this value in the evaluate state. With the latching device, this value is not affected by the first precharged node once the circuit has sufficiently transitioned to the evaluate state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.