Semiconductor memory device preventing erroneous writing in write operation and delay in read operation
US6584005B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2002 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Nov 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.