Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US6586276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jul 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.