Graded/stepped silicide process to improve mos transistor
US6586320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Nov 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.