Deep submicron silicide blocking
US6586332B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Oct 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for blocking formation of a reacted metal layer on a structure in an integrated circuit. The integrated circuit has a source region, a drain region, a gate, an isolation area formed of a material, and a protective layer formed of substantially the same material as the isolation area. The protective layer overlies at least the source region and the drain region. The method is accomplished while reducing an amount of the material of the isolation area that is removed when the material of the protective layer is removed. A blocking layer is deposited on the integrated circuit. The blocking layer is formed of a material that is substantially different from the material of the isolation area and the protective layer. The blocking layer is patterned to selectively cover portions of the blocking layers that overlie at least the structure and selectively expose portions of the blocking layer that overlie at least the source region, the drain region, and the gate. The exposed portions of the blocking layer are etched with an etchant to substantially remove the exposed portions of the blocking layer, and to expose portions of the protective layer. The etchant etches the blocking lay…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.