Wafer-level antenna effect detection pattern for VLSI
US6586765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2002 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Feb 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test structure for evaluating plasma damage in thin gate oxides is formed with a single polysilicon floating gate EEPROM device on which an antenna structure delivers charge to a floating gate through a tunnel oxide. The floating gate extends beyond the MOSFET channel in one direction, passing over field oxide and terminating in a pad over a thin tunnel oxide window formed over an isolated n+ diffusion. The n+ diffusion is connected to a metal antenna structure which is exposed to a processing plasma. Charge accumulated on the antenna during plasma exposure causes a tunnel current to flow through the tunnel oxide, and charge to accumulate on the floating gate. A second extension of the polysilicon floating gate passes over a second field oxide region and terminates in a pad over a thicker oxide formed on a second isolated n+ diffusion. The second n+ diffusion forms the control gate of the EEPROM and is connected by wiring to a probe pad. The device is formed in the saw-kerf region of a product wafer. After exposure of the device to plasma processing, the device is tested in-line with conventional probe testing equipment. Threshold voltage is measured by applying a scanning voltag…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.