Integrated core microelectronic package
US6586822B1 · kind B1 · utility
122Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Sep 8, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4935
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.