Integrated circuit bus grid having wires with pre-selected variable widths
US6586828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Oct 17, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical bus grid (108) for an application specific integrated circuit (ASIC) chip (102). The bus grid is generally formed by mutually orthogonal wires (28′, 30′) contained within two metal layer (M6′, M7′). The bus grid is located within each of a plurality of contiguous rectangular regions (32′), which are defined by electrical contacts (12′). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular regions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., 18, 20, 22) within the ASIC chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.