Method and circuit for testing DC parameters of circuit input and output nodes
US6586921B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and built-in circuit are described for testing direct current (DC) parameters of the input and output pins of a circuit by testing the transition time interval for rising and falling voltage transitions. When the voltage transition is for an integrated circuit (IC) pin having a known capacitance, which can include off-chip capacitance, the magnitude and direction of current at the pin can be determined. The method enables testing an IC via a test access port (TAP) comprising a subset of the pins of the IC, for example in conformance with the IEEE 1149.1 boundary scan test standard. For sufficiently small current magnitudes, such as leakage current (IIL and IIH), the technique can use only on-chip circuitry to sample a pin voltage at time intervals after an output transition is generated at the pin, the time intervals pre-determined to be less than the transition time interval. For larger current magnitudes, such as IOL and IOH, an off-chip capacitance of known value is connected to the pin to decrease the rate of transition. For greater accuracy, an off-chip resistor of known value is connected to the pin, and the transition time interval due to the driver is compared to t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.