Nonlinear digital differential amplifier offset calibration
US6586989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Nov 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods for calibrating offset error in a differential amplifier in an efficient and reliable way are described. A final calibrated state for the differential amplifier is obtained in accordance with a nonlinear search that requires significantly fewer test stages to complete than linear search methods. As a result, longer test periods may be used with the invention without adversely affecting the overall length of the calibration process. Because circuit conditions near the calibration point cause internal test signals to switch more slowly from one state to another, lengthening the test period time may allow more time for the internal test signals to reach their final values and, thereby, improve calibration accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.