Capacitor bias recovery methodology
US6587296B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Sep 11, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/4984
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A preamplifier circuit for a hard disk drive system comprises a preamplifier circuit having a bias voltage circuit stage associated therewith. The preamplifier circuit further comprises a current bias boost recovery circuit operatively coupled to the bias voltage circuit stage which is configured to increase a rate of charging of a noise reduction capacitor associated with the bias voltage circuit stage. A head select boost recovery circuit is also operatively coupled to the bias voltage circuit and is configured to increase a rate of charging or discharging of a bias capacitor associated with the bias voltage circuit stage. Together the circuits allow for a concurrent head switch and current bias switch and avoids the problems associated with the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.