Memory device with multi-level storage cells and apparatuses, systems and methods including same
US6587372B2 · kind B2 · utility
31Cited by
14References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jan 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention comprises memory devices, apparatuses and systems including multiple bit per cell memory cells and methods for operating same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.