Dynamic data bus allocation
US6587905B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Dec 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged. A corresponding Auxiliary_(read or write) command is routed to the slave units to notify the units when to route normal read or write data to an idle bus. The bus controller may use this added feature to optimize the available bandwidth of independent read and write data busses up to the limit where a read or write ba…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.