Method of partitioning large transistor design to facilitate transistor level timing
US6588000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Aug 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level. The method comprises the steps of identifying a desired number of blocks for the second hierarchical level, representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary, and identifying transistor networks that extend across block boundaries. The method further comprises the steps of assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and re-assigning some of the transistors among the blocks to reduce the maximum number of transistors in any one block. Preferably, the transistors are assigned from one block to another by identifying partitions for groups of transistors; and then reassigning assigning transistors on the basis of said partitions. For example, the transistors may be partitioned on the basis of functionality, by name, to minimize connectivity, or to duplicate pre-existing hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.