EEPROM cell testing circuit
US6590256B2 · kind B2 · utility
0Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 23, 1999 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Nov 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A testing circuit made on a silicon wafer including a plurality of identical cells, each of which includes a primary capacitor of given characteristics, which includes a test capacitor of same characteristics as each primary capacitor and of surface at least equal to the sum of the surfaces of the primary capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.