SIO stacked DRAM logic

US6590258B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ramachandra Divakauni · Somers, US
• Mark C. Hakey · Saint Albans, US
• William H. Ma · Wappingers Falls, US
• Jack A. Mandclman · Stormville, US
• William R. Tonti · South Burlington, US

Key dates

• Filing date: Dec 3, 2001
• Grant date: Jul 8, 2003
• Expiry date: Dec 3, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/94
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.