Crack-preventive semiconductor package
US6590281B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jan 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding portion. A wire bonding region and a bump attach region are respectively defined on opposite surfaces of the protruding portion, and staggered in position. This allows a force applied from a wire bonder to the wire bonding regions not to adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions spaced apart from the bump attach regions can be prevented from being contaminated by an etching solution used in solder bump implantation, so that wire bonding quality can be well maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.