Method and apparatus for soft defect detection in a memory
US6590818B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jun 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for soft defect detection in a memory is disclosed. Bit lines are conditioned to predetermined voltages which ensure that, upon activation of the corresponding word line, all the storage transistors within the corresponding bit cells (at the intersection of the bit lines and the word line) are electrically conductive. A change in state of the bit cell in response to activation of the corresponding word line indicates the presence of a soft defect. An evaluator coupled to the memory may be used to identify defective memories by comparing the results of the testing to determine if any bit cells changed states. In one embodiment, the conditioning of the bit lines includes charging a bit line to a first predetermined voltage and its corresponding complementary bit line to a second predetermined voltage and then connecting the bit line and complementary bit line together to equalize the voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.