Digit line equilibration using time-multiplexed isolation
US6590819B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Mar 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and apparatus for equilibrating paired digit lines and sense amplifier input of a memory device, particularly useful where one side of a memory array contains a defect. A pair of isolation circuits is arranged on either side of a sense amplifier between the sense amplifier and respective digit lines pairs from two memory arrays. By selectively enabling one and then the other of the isolation circuits in a multiplexed fashion, the single equilibrate circuit located between one of the isolation circuits of the sense amplifier can separately and sequentially equilibrate both pairs of digit lines. In addition, both isolation circuits can be disabled isolating the sense amplifier from all digit lines allowing the sense amplifier to be separately equilibrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.