Apparatus and method for tracking flushes of cache entries in a data processing system
US6591332B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method using a valid bit in a cache entry address first-in-first-out (FIFO) to indicate when a cache entry can be flushed in a coherent memory domain. One embodiment of the invention involves a method for tracking a cache entry in a cache serving data transfers between a coherent memory domain and a non-coherent memory domain in a data processing system, including steps of storing an address corresponding to a cache entry in a FIFO register, using at least one register cell as a valid flag to indicate when the cache entry is still in the cache, and changing the valid flag based on one or more signals transmitted from the non-coherent memory domain. A second embodiment of the invention involves a data processing system or an I/O bridge host, having a cache and multiple cache entries, serving data transfers between a coherent memory domain and a non-coherent memory domain, including registers configured to store an address corresponding to a cache entry, wherein each FIFO register has a valid flag to indicate when the cache entry is still in the cache, and the valid flag can be changed based on one or more signals transmitted from the non-coherent memory domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.