Microprocessor having improved memory management unit and cache memory
US6591340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jun 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted. If the memory access operation is not permitted by the permission information of the particular entry of the virtual cache memory, then the translation lookaside buffer may be accessed based on the logical address information of the particular entry of the virtual cache memory. If there is a match between the logical address information of the particular e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.