Mark Debbage
20Patents
4h-index
35Co-inventors
63Inventor score
Filing activity: Oct 1, 1999 → Jun 29, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6412043B1 | Microprocessor having improved memory management unit and cache memory | Physics | 48 | Expired |
| US6591340B2 | Microprocessor having improved memory management unit and cache memory | Physics | 29 | Expired |
| US7543132B1 | Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes | Physics | 11 | Expired |
| US6553460B1 | Microprocessor having improved memory management unit and cache memory | Physics | 8 | Expired |
| US9477631B2 | Optimized credit return mechanism for packet sends | Physics | 3 | Active |
| US9391845B2 | System, method and apparatus for improving the performance of collective operations in high performance computing | Electricity | 2 | Active |
| US9460019B2 | Sending packets using optimized PIO write sequences without SFENCEs | Physics | 2 | Active |
| US10015056B2 | System, method and apparatus for improving the performance of collective operations in high performance computing | Electricity | 2 | Active |
| US12190405B2 | Direct memory writes by network interface of a graphics processing unit | Physics | 1 | Active |
| US10044626B2 | Reliable out-of order end-to-end protocol with robust window state overflow management and a multi-node system using same | Electricity | 1 | Active |
| US9792235B2 | Optimized credit return mechanism for packet sends | Physics | 0 | Active |
| US11467885B2 | Technologies for managing a latency-efficient pipeline through a network interface controller | Emerging Cross-Sectional Technologies | 0 | Active |
| US9785359B2 | Sending packets using optimized PIO write sequences without sfences and out of order credit returns | Physics | 0 | Active |
| US9984020B2 | Optimized credit return mechanism for packet sends | Physics | 0 | Active |
| US10073796B2 | Sending packets using optimized PIO write sequences without SFENCES | Physics | 0 | Active |
| US12137001B2 | Scalable protocol-agnostic reliable transport | Electricity | 0 | Active |
| US9734077B2 | Sending packets using optimized PIO write sequences without sfences | Physics | 0 | Active |
| US12212502B2 | Reliable transport architecture | Electricity | 0 | Active |
| US9588899B2 | Sending packets using optimized PIO write sequences without sfences | Physics | 0 | Active |
| US12177277B2 | System, apparatus, and method for streaming input/output data | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.