Masking error detection/correction latency in multilevel cache transfers
US6591393B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus mask the latency of error detection and/or error correction applied to data transferred between a first memory and a second memory. The method comprises determining whether there is an error in a data unit in the first memory; transferring data based on the data unit from the first memory to a second memory, wherein the transferring step commences before completion of the determining step; and disabling at least part of the second memory if the determining step detects an error in the data unit. The disabling step may be accomplished, for example, by disabling the buffering of an address of the data unit or stalling the second memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.