Measuring integrated circuit layout efficiency
US6591409B2 · kind B2 · utility
5Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Nov 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of measuring layout efficiency is disclosed wherein after the initial layout (A), and the layout is drawn (B) a layout verification step C includes identifying seed devices or layers and the devices or layers are grown according to design rules and process rules to determine the minimum area required for the design. The layout verification is performed for both device packing density and interconnect packing density and the efficiency is calculated based on the total available area and reported.(D).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.