Pillar connections for semiconductor chips and method of manufacture
US6592019B2 · kind B2 · utility
167Cited by
13References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2001 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Apr 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip chip interconnect system comprises an elongated pillar comprising two elongated portions, a first portion including solder with or without lead and a second portion including copper or gold or other material having a higher reflow temperature than the first portion. The second portion is to be connected to the semiconductor chip and has a length preferably of more than 55 microns to reduce the effect of &agr; particles from the solder from affecting electronic devices on the chip. The total length of the pillar is preferably in the range of 80 to 120 microns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.