ADVANPACK SOLUTIONS PTE LTD.
45Patents
31Active
45Granted
49Portfolio score
Filing activity: Apr 27, 2000 → Sep 19, 2018 · 12 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6578754B1 | Pillar connections for semiconductor chips and method of manufacture | Electricity | 392 | Expired |
| US6550666B2 | Method for forming a flip chip on leadframe semiconductor package | Electricity | 210 | Expired |
| US6592019B2 | Pillar connections for semiconductor chips and method of manufacture | Electricity | 167 | Expired |
| US7462942B2 | Die pillar structures and a method of their formation | Electricity | 136 | Expired |
| US6681982B2 | Pillar connections for semiconductor chips and method of manufacture | Electricity | 108 | Expired |
| US6510976B2 | Method for forming a flip chip semiconductor package | Electricity | 57 | Expired |
| US6732913B2 | Method for forming a wafer level chip scale package, and package formed thereby | Electricity | 55 | Expired |
| US7087458B2 | Method for fabricating a flip chip package with pillar bump and no flow underfill | Electricity | 55 | Expired |
| US7456496B2 | Package design and method of manufacture for chip grid array | Electricity | 40 | Active |
| US6750082B2 | Method of assembling a package with an exposed die backside with and without a heatsink for flip-chip | Electricity | 33 | Expired |
| US7795071B2 | Semiconductor package for fine pitch miniaturization and manufacturing method thereof | Electricity | 28 | Active |
| US6734039B2 | Semiconductor chip grid array package design and method of manufacture | Emerging Cross-Sectional Technologies | 23 | Expired |
| US6929981B2 | Package design and method of manufacture for chip grid array | Electricity | 23 | Expired |
| US6599775B2 | Method for forming a flip chip semiconductor package, a semiconductor package formed thereby, and a substrate therefor | Electricity | 23 | Expired |
| US6467676B1 | Fluxing adhesive | Electricity | 20 | Expired |
| US8207608B2 | Interconnections for fine pitch semiconductor devices and manufacturing method thereof | Electricity | 17 | Active |
| US6365435B1 | Method for producing a flip chip package | Emerging Cross-Sectional Technologies | 17 | Expired |
| US9653323B2 | Manufacturing method of substrate structure having embedded interconnection layers | Electricity | 8 | Active |
| US8709874B2 | Manufacturing method for semiconductor device carrier and semiconductor package using the same | Emerging Cross-Sectional Technologies | 3 | Active |
| US9219027B2 | Semiconductor device carrier and semiconductor package using the same | Emerging Cross-Sectional Technologies | 2 | Active |
| US9301391B2 | Substrate structure, semiconductor package device, and manufacturing method of substrate structure | Electricity | 2 | Active |
| US9136215B2 | Manufacturing method for semiconductor package | Electricity | 2 | Active |
| US8846519B2 | Interconnections for fine pitch semiconductor devices and manufacturing method thereof | Electricity | 1 | Active |
| US9379044B2 | Package carrier, package carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof | Electricity | 1 | Active |
| US9892916B2 | Manufacturing method of package substrate and package manufacturing method of semiconductor device | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.