Design and processing of antifuse structure
US6593172B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2001 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | May 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition, in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected. The result is an antifuse that is well isolated from other wiring and a standard via that will facilitate good electrical contact between metal layer 1 and 2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.