Method for adding features to a design layout and process for designing a mask

US6593226B2 · kind B2 · utility

Assignee

• Motorola, Inc. · US

Inventors

• Edward O. Travis · Austin, US
• Aykut Dengi · Tempe, US
• Sejal Chheda · Austin, US
• Tat-Kwan Yu · Cupertino, US
• Mark S. Roberton · Los Angeles, US
• Ruiqi Tian · Pflugerville, US
• Robert Boone · Grenoble, FR
• Alfred J. Reich · Austin, US

Key dates

• Filing date: Jul 17, 2001
• Grant date: Jul 15, 2003
• Expiry date: Dec 30, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/926
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).