Two step chemical mechanical polishing process
US6593240B1 · kind B1 · utility
54Cited by
13References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 28, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Dec 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A method for polishing a semiconductor wafer includes providing a semiconductor wafer having topographical features and forming a dielectric layer on the semiconductor wafer to fill portions between the features. The dielectric layer is planarized across the entire semiconductor wafer for a first portion of a polishing process. The dielectric layer is polished for bulk removal of the dielectric layer for a remaining portion of the polishing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.