Field effect transistors with vertical gate side walls and method for making such transistors

US6593617B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Diane C. Boyd · Lagrangeville, US
• Stuart M. Burns · Ridgefield, US
• Hussein I. Hanafi · Berkeley Heights, US
• Yuan Taur · Bedford, US
• William C. Wille · Red Hook, US

Key dates

• Filing date: Feb 19, 1998
• Grant date: Jul 15, 2003
• Expiry date: Jan 15, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0225

Abstract

Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt.Such an FET can be made using the following method:forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer;defining an etch window having the lateral size and shape of a gate pillar to be formed;defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process;depositing a gate conductor such that it fills the gate hole;removing the gate conductor covering the portions of the dielectric stack surrounding the gate hole;removing at least part of the dielectric stack such that a gate pillar with vertical side walls is set free.