Method and apparatus for low power domino decoding
US6593776B2 · kind B2 · utility
1Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.