Multi-port memory device and system for addressing the multi-port memory device
US6594196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Jun 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated. A system for addressing the multi-port memory array includes a conflict detector for detecting a conflict between two or more of the row address signals to generate a conflict control signal corresponding to the conflict detected, a priority logic circuit for performing a logic operation with respect to the request command signals based on a predetermined priority logic to generate prioritized signals, and a selection unit for selecting one of a request c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.