Cache memory with dual-way arrays and multiplexed parallel output
US6594728B1 · kind B1 · utility
79Cited by
27References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 7, 1997 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Mar 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilities the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.