Prefetch system for memory controller
US6594730B1 · kind B1 · utility
19Cited by
13References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1999 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Aug 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides a memory controller that includes a plurality of transaction queues and an arbiter, a prefetch cache in communication with the arbiter, and a prefetch queue in communication with the prefetch cache. The prefetch queue also may be provided in communication with each of the transaction queues for the purpose of determining whether the transaction queues are operating in a congested state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.