System and method for semaphore and atomic operation management in a multiprocessor
US6594736B1 · kind B1 · utility
31Cited by
11References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 15, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Oct 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus including a plurality of data processing units. A plurality of memory banks having a shared address space are coupled to the processors by a crossbar coupling to enable reading and writing data between the processors and memory banks. A unidirectional network couples the memory banks and the processors to enable cache coherency messages to be transmitted from the memory to the processors. A plurality of semaphore registers are implemented within the shared address space of the memory banks wherein the semaphore registers are accessible by the processors through the crossbar coupling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.