Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters
US6594754B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1999 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Jul 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture to process move instructions by allowing multiple mappings between logical registers and the same physical register. In one embodiment, a counter is associated with each physical register to indicate when the physical register is free. A register-to-register move instruction is processed by mapping the logical destination register of the move instruction to the same physical register to which the logical source register of the move instruction is mapped. An immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register storing the immediate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.