Cell architecture with local interconnect and method for making same
US6594813B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Jul 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit. In a preferred embodiment, the local interconnect metallization lines are configured to be fabricated from a higher resistivity metal having a resistivity that is greater than aluminum contai…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.