Memory architecture permitting selection of storage density after fabrication of active circuitry
US6594818B2 · kind B2 · utility
20Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2001 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | May 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/01
Abstract
A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity. The specialized layer can be formed using different masks sets that form a different conductive pattern for each storage capacity or forming a generic interconnect structure with fuses that are cut to select the storage capacity of the memory chips
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.