Method of making wafer level packaging and chip structure
US6596560B1 · kind B1 · utility
19Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 3, 2002 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | May 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
FILE: 8289USF.RTF19A chip structure comprises a wafer, an insulation layer, some conductive paste, a plurality of ball pads, a solder mask and a plurality of solder balls. The wafer has an active surface. The insulation layer is formed over the active surface of the wafer. The insulation layer has a plurality of open windows. The conductive paste fills the open windows. The ball pads are formed over the insulation layer in electrical connection with the conductive paste. The solder mask formed over the insulation layer. The solder mask exposes the ball pads. A solder ball is mounted to each ball pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.