Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure
US6596580B2 · kind B2 · utility
7Cited by
5References
7Claims
0Family size
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Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Oct 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.