Increased solder-bump height for improved flip-chip bonding and reliability
US6596618B1 · kind B1 · utility
14Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Dec 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of forming solder bumps on a semiconductor chip, for flip-chip bonding, having increased height to improve the solder joint reliability of the flip-chip bonded chip and carrier assembly. According to the present invention, a second layer of solder structure is deposited on to each of the solder bump precursor structures formed by a first layer of solder structure to increase the solder-bump volume, which results in solder bumps with increased height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.